SPORT Programming Examples
5-88 ADSP-21368 SHARC Processor Hardware Reference
SPORT_DMA_setup:
/* set internal loopback bit for SPORT2 & SPORT3 */
bit set ustat3 SPL;
dm(SPMCTL2) = ustat3;
/* Configure SPORT2 as a transmitter */
/* internally generating clock and frame sync */
/* CLKDIV = [fCCLK(333MHz)/2 x FSCLK(8.325 MHz)] – 1 = 0x0004 */
/* FSDIV = [FSCLK(8.325 MHz)/TFS(.26 MHz)] – 1 = 31 = 0x001F */
R0 = 0x001F0004; dm(DIV2) = R0;
ustat4 = SPEN_A| /* Enable Channel A */
SLEN32| /* 32-bit word length */
FSR| /* Frame Sync Required */
SPTRAN| /* Transmit on enabled channels */
IFS| /* Internally Generated Frame Sync */
ICLK; /* Internally Generated Clock */
dm(SPCTL2) = ustat4;
/* Configure SPORT3 as a receiver */
/* externally generating clock and frame sync */
r0 = 0x0; dm(DIV3) = R0;
ustat3 = SPEN_A| /* Enable Channel A */
SLEN32| /* 32-bit word length */
FSR; /* Frame Sync Required */
dm(SPCTL3) = ustat3;
/* Set up loop to transmit and receive data */
lcntr = LENGTH(tx_buf2a), do (pc,4) until lce;
/* Retrieve data using DAG1 and send TX via SPORT2 */
r0 = dm(i4,m4);
dm(TXSP2A) = r0;
/* Receive data via SPORT3 and save via DAG2 */
r0 = dm(RXSP3A);
pm(i12,m12) = r0;
_main.end: jump (pc,0);
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