External Memory Interface
3-8 ADSP-21368 SHARC Processor Hardware Reference
The following example shows the innermost loop of a FIR filter.
lcntr=FILTER_TAPS-1, do macloop until lce;
macloop: f12=f0*f4, f8=f8+f12, f0=dm(i0,m1), f4=pm(i9,m9);
In this example, if the code is stored and executed from external memory,
the first time through this loop the program sequencer places the appro-
priate 24-bit address on the external address bus, and fetches the
instruction in line 2 from external memory. While this instruction is being
fetched and processed by the sequencer, it is also simultaneously stored in
the internal instruction cache.
For every subsequent iteration of this loop, the instruction is fetched from
the internal cache, thereby occurring in a single cycle, while freeing up the
internal memory buses to fetch the data operands required for the
instruction.
Previously, in the absence of the internal instruction cache, the number of
cycles taken by the loop for a case of FILTER_TAPS = 16 would have been a
minimum of 48 cycles over a 16-bit wide external bus, and 24 cycles over
a 32-bit wide external bus (excluding any conflicts for data operand
fetches). However, with the presence of the instruction cache, and assum-
ing that the execution is from external SDRAM, and that the instructions
are on the same SDRAM page, the number of cycles is reduced to 17 over
a 16-bit wide external bus, and either 15 cycles or 16 cycles over a 32-bit
wide bus (depending on whether instruction 1 begins on an even 32-bit
address, or odd 32-bit address).
Thus, the internal cache improves the efficiency of execution from 16-bit
wide external memory by approximately 64.5% for this example.
As might be expected, it is important to remember that the instruction
cache will not play a significant role in improving the efficiency of strictly
linearly executed code from external memory.
To Next Page
Loading...
Need help?
General
