ADSP-21368 SHARC Processor Hardware Reference A-13
Register Reference
18–15 DATE Data Enable.
In no pack mode of the sdram/ami memory controller,
masks those bits of the data lane with zeros. The data
lane is 8 bits. The 32-bit data bus has four data lanes.
DATA31–0 is mapped to {dl3, dl2, dl1, dl0}
For example, If DATE is 1010, then dl3 and dl1 are
masked with zeros.
31–19 Reserved
Table A-3. EPCTL Register Bit Descriptions (Cont’d)
Bit Name Description
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