ADSP-21368 SHARC Processor Hardware Reference 2-5
I/O Processor
In addition to the above, the following situations incur additional stall
cycles.
1. An aborted conditional I/O processor register read can cause one or
two extra core-clock stall cycles if it immediately follows a write.
Such a read is expected to take three core cycles, but it takes four or
five.
2. In case of a full write FIFO, the held-off I/O processor register read
or write access incurs one extra core-clock cycle.
3. Interrupted reads and writes, if preceded by another write, creates
an additional one core cycle stall.
Inside of an interrupt service routine (ISR), a write into an IOP register
that clears the interrupt has some latency. During this delay, the interrupt
may be generated a second time if the program executes an
RTI
instruction.
For example, in the following code the interrupt isn’t cleared instanta-
neously. During the delay, if the program comes out of the ISR, the
interrupt is generated again.
/*.... code .....*/
dm(TXSPI) = R0; /* Write to TXSPI FIFO; disable spi;
clears the interrupt */
rti;
DMA1S/E Data memory breakpoint address number
1 start/end
0x300B2/
0x300B3
DMA2S/E Data memory breakpoint address number
2 start/end
0x300B3/
0x300B4
PMDAS/E Program memory breakpoint address
start/end
0x300B8/
0x300B9
Table 2-2. Memory-Mapped Emulation/Breakpoint Registers (Cont’d)
Register Description Address
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