Parallel Data Acquisition Port (PDAP)
7-8 ADSP-21368 SHARC Processor Hardware Reference
Parallel Data Acquisition Port (PDAP)
The input to channel 0 of the IDP is multiplexed, and may be used either
in the serial mode, described in “Serial Inputs” on page 7-3, or in a direct
parallel input mode. Serial or parallel input is selected by setting
IDP_PDAP_EN bit 31 in the IDP_PP_CTL register. When used in parallel
mode, the clock input for channel 0 is used to latch parallel subwords.
Multiple latched parallel subword samples may be packed into 32-bit
words for efficiency. The frame sync input is used to hold off latching of
the next sample (that is, ignore the clock edges). The data then flows
through the FIFO and is transferred by a dedicated DMA channel into the
core’s memory as with any IDP channel. As shown in Figure 7-12, the
PDAP can accept input words up to 20 bits wide, or can accept input
words that are packed as densely as 4 input words up to 8 bits wide.
The
IDP_PP_CTL register also provides a reset bit that zeros any data that is
waiting in the packing unit to be latched into the FIFO. When asserted,
the
IDP_PDAP_RESET bit (bit 30 in the IDP_PP_CTL register) causes the reset
circuit to strobe, then automatically clear itself. Therefore, this bit always
returns a value of zero when read. The
IDP_PORT_SELECT bit
Figure 7-12. Parallel Data Acquisition Port (PDAP) Functions
DATA[31:12]
DAI PINS
[20:1]
IDP_PORT_SELECT
(IDP_PP_CTL[26])
1
[19:0]
MASK
20
IDP_Pxx_MASK
(IDP_PP_CTL[19:0])
20
PACKING
UNIT
IDP_PP_PACKING
(IDP_PP_CTL[28:27])
2
SERIAL
INPUT
29
32
IDP_PP_EN
(IDP_PP_CTL[31])
32
TO
FIFO
20
1
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