Analog Devices SHARC ADSP-21368 User Manual

SDRAM Controller
3-50 ADSP-21368 SHARC Processor Hardware Reference
To calculate the value to write to the
SDRRC register, use the following
equation.
Where:
f
SDCLK
= SDCLK frequency (SDRAM clock frequency)
t
REF
= SDRAM refresh period
NRA = Number of row addresses in SDRAM (refresh cycles to
refresh whole SDRAM)
t
RAS
= Active to precharge time (SDTRAS bits in the SDRAM mem-
ory control register) in number of clock cycles
t
RP
= RAS to precharge time (in the SDRAM memory control reg-
ister) in number of clock cycles
This equation calculates the number of clock cycles between required
refreshes and subtracts the required delay between bank activate com-
mands to the same bank (t
RC
= t
RAS
+ t
RP
). The t
RC
value is subtracted, so
that in the case where a refresh time-out occurs while an SDRAM cycle is
active, the SDRAM refresh rate specification is guaranteed to be met. The
result from the equation is always rounded down to an integer. Below is
an example of the calculation of
RDIV for a typical SDRAM in a system
with a 133 MHz SDRAM clock.
f
SDCLK
= 133 MHz
t
REF
= 64 ms
NRA = 8192 row addresses
t
RAS
= 6
t
RP
= 3
RDIV
f
SDCLK
t
REF
×
NRA
-----------------------------------
⎠
⎞
t
RAS
(– t
RP
)+
⎝
⎛
≤

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP