Enhanced Emulation Status Register
A-182 ADSP-21368 SHARC Processor Hardware Reference
11 EEMUOUTFULL Enhanced Emulation EEMUOUT FIFO Status.
3
0 = EEMUOUT FIFO is not full
1 = EEMUOUT FIFO full
12 EEMUINFULL Enhanced Emulation EEMUIN Register Status.
4
0 = EEMUIN register is empty
1 = EEMUIN register full
13 EEMUENS Enhanced Emulation Feature Enable.
4
0 = Enhanced emulation feature enable
1 = Enhanced emulation feature disable
14 OSPIDENS OSPID Register Enable.
4
0 = OSPID register enable
1 = OSPID register disable
15 EEMUINENS EEMUIN Interrupt Enable.
4
0 = EEMUIN interrupt disable
1 = EEMUIN interrupt enable
16 STATIOY IOY Memory Breakpoint Status
0 = No breakpoint occurs
1 = Breakpoint occurs
31–17 Reserved
1 Internal hardware sets this bit.
2 This bit is set and reset by the core.
3 The FIFO controller sets and resets this bit.
4 Internal hardware sets and resets this bit.
Table A-72. EEMUSTAT Register Bit Descriptions (Cont’d)
Bit Name Description
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