ADSP-21368 SHARC Processor Hardware Reference xxxiii
Preface
• Chapter 8, “Pulse Width Modulation”
Describes the implementation and use of the pulse width modula-
tion module which provides a technique for controlling analog
circuits with the microprocessor’s digital outputs.
• Chapter 9, “S/PDIF Transmitter/Receiver”
Provides information on the use of the Sony/Philips Digital Inter-
face which is a standard audio file transfer format that allows the
transfer of digital audio signals from one device to another without
having to be converted to an analog signal.
• Chapter 10, “Asynchronous Sample Rate Converter”
Provides information on the sample rate converter module. This
module performs synchronous or asynchronous sample rate conver-
sions across independent stereo channels, without using any
internal processor resources.
• Chapter 11, “UART Port Controller”
Describes the operation of the Universal Asynchronous
Receiver/Transmitter (UART) which is a full-duplex peripheral
compatible with PC-style industry-standard UART.
• Chapter 12, “Two Wire Interface Controller”
The two wire interface is fully compatible with the widely used I
2
C
bus standard. It is designed with a high level of functionality and is
compatible with multi-master, multi-slave bus configurations.
• Chapter 13, “Precision Clock Generators”
Details the precision clock generators (PCG) each of which gener-
ates a pair of signals derived from a clock input signal.
• Chapter 14, “System Design”
Describes system design features of the ADSP-21367/8/9 and
ADSP-2137x processors. These include power, reset, clock, JTAG,
and booting, as well as pin descriptions and other system level
information.
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