ADSP-21368 SHARC Processor Hardware Reference 5-91
Serial Ports
_main:
// SPORT Loopback: Use SPORT0 as RX & SPORT1 as TX //
/* initially clear SPORT control register */
r0 = 0x00000000;
dm(SPCTL0) = r0;
dm(SPCTL1) = r0;
dm(SPMCTL1) = r0;
SPORT_DMA_setup:
/* set internal loopback bit for SPORT0 & SPORT1 */
bit set ustat3 SPL;
dm(SPMCTL1) = ustat3;
/* Configure SPORT1 as a transmitter */
/* internally generating clock and frame sync */
/* CLKDIV = [fCCLK(333 MHz)/8xFSCLK(8.325 MHz)]-1 = 0x0004 */
/* FSDIV = [FSCLK(8.325 MHz)/TFS(.26 MHz)]-1 = 31 = 0x001F */
R0 = 0x001F0004; dm(DIV1) = R0;
ustat4 = SPEN_A| /* Enable Channel A */
SLEN32| /* 32-bit word length */
FSR| /* Frame Sync Required */
SPTRAN| /* Transmit on enabled channels */
SDEN_A| /* Enable Channel A DMA */
SCHEN_A| /* Enable Channel A DMA Chaining */
IFS| /* Internally-generated Frame Sync */
ICLK; /* Internally-generated Clock */
dm(SPCTL1) = ustat4;
/* Configure SPORT0 as a receiver */
/* externally generating clock and frame sync */
r0 = 0x0; dm(DIV0) = R0;
ustat3 = SPEN_A| /* Enable Channel A */
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