SPI Data Transfer Operations
6-22 ADSP-21368 SHARC Processor Hardware Reference
configuration. In this case, the slave is always selected. Data cor-
ruption can be avoided by enabling the slave only after configuring
both the master and slave devices.
When performing transmit operations with the SPI port, disabling the SPI
port prematurely can cause data corruption and/or faulty transmission.
Before the program disables the SPI port in order to reconfigure it, the
status bits should be polled to ensure that all valid data has been com-
pletely transferred. For core-driven transfers, data moves from the
TXSPI
buffer into a shift register. The following bits should be checked before
disabling the SPI port:
1. Wait for the TXSPIx buffers to empty into the shift register. This is
done when the TXS bit (bit 3) of the SPISTATx registers becomes
zero.
2. Wait for the SPI shift registers to finish shifting out data. This is
done when the SPIF bit (bit 0 of SPISTATx registers) becomes one.
3. Disable the SPI ports by setting the SPIEN bit (bit 0) in the SPICTLx
registers to zero.
When performing transmit DMA transfers, data moves through a
four-deep SPI DMA FIFO, then into the TXSPIx buffers, and finally into
the shift register. DMA interrupts are latched when the I/O processor
moves the last word from memory to the peripheral. For the SPI, this
means that the SPI “DMA complete” interrupt is latched when there are
still six words yet to be fully transmitted (four in the FIFO, one in the
TXSPIx buffers, and one being shifted out of the shift register). To disable
the SPI port after a DMA transmit operation, use the following steps:
1. Wait for DMA FIFO to empty. This is done when the
SPISx bits
(bits 13–12 in the
SPIDMACx registers) become zero.
2. Wait for the
TXSPIx registers to empty. This is done when the TXS
bit (bit 3) in the SPISTATx registers) becomes zero.
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