Analog Devices SHARC ADSP-21368 - Page 411

ADSP-21368 SHARC Processor Hardware Reference 6-39
Serial Peripheral Interface Ports
Listing 6-1. SPI Master Mode Core-Driven Transmit
/* SPI Control Registers */
#define SPICTL (0x1000)
#define SPIFLG (0x1001)
#define SPIBAUD (0x1005)
#define TXSPI (0x1003)
/*SPICTL bits*/
#define TIMOD1 (0x0001) /* Use TX buffer for transfers */
#define DMISO (0x0020) /* Disable MISO pin */
#define WL32 (0x0100) /* SPI Word Length = 32 */
#define SPIMS (0x1000) /* SPI Master if 1, Slave if 0 */
#define SPIEN (0x4000) /* SPI port Enable */
/*SPIFLG bits */
#define DS0EN (0x0001) /* use FLG0 as SPI device-select*/
/* Default Buffer Length */
#define BUFSIZE 10
.SECTION/DM seg_dmda;
/* Transmit Buffer */
.var tx_buf[BUFSIZE] = 0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888,
0x99999999,
0xAAAAAAAA;