ADSP-21368 SHARC Processor Hardware Reference 8-23
Pulse Width Modulation
/* PWM enables */
PWM_enables:
ustat3=dm(SYSCTL); /* System Control Register */
bit set ustat3 PWM0EN | PPFLGS;
dm(SYSCTL)=ustat3; /* Selects AD11–8 in PWM0 mode instead
of PP mode */
ustat3=dm(PWMSEG0); /* PWM Output Enable. Should probably be
changed to PWM Output Disable since you
write it to disable it. */
bit set ustat3 PWM_BH | PWM_BL; /* disables B outputs */
dm(PWMSEG0)=ustat3;
ustat3=dm(PWMCTL0); /* PWM0 Control Register
ustat3=0;
dm(PWMCTL0)=ustat3; /* Enables edge-aligned, individual pair
mode with single update and no
interrupt */
ustat3=dm(PWMGCTL); /* PWM General Control Register */
bit set ustat3 PWM_EN0 | PWM_DIS1 | PWM_DIS2 | PWM_DIS3 |
PWM_SYNCEN0 | PWM_SYNCDIS1| PWM_SYNCDIS2| PWM_SYNCDIS3;
dm(PWMGCTL)=ustat3; /* Enables only PWM 0 and its internal
timer; Disables other PWMs globally. The
write to PWMGCTL will kick off the
transfer */
PWM_enables.end: rts;
idle
;
To Next Page
Loading...
Need help?
General
