ADSP-21368 SHARC Processor Hardware Reference xiii
Contents
SPORT Programming Examples .................................................. 5-82
SERIAL PERIPHERAL INTERFACE PORTS
Functional Description ................................................................. 6-2
SPI Interface Signals ..................................................................... 6-4
SPI Clock Signal (SPICLK) ..................................................... 6-4
SPICLK Timing .................................................................. 6-5
SPI Slave Select Input (SPIDS) ............................................ 6-6
SPI Flag Signals (SPIFLG3-0) .................................................. 6-6
Master Out Slave In (MOSI) ................................................... 6-7
Master In Slave Out (MISO) ................................................... 6-7
SPI General Operations ................................................................. 6-8
SPI Enable .............................................................................. 6-9
Open Drain Mode (OPD) ....................................................... 6-9
Master Mode Operation ........................................................ 6-10
Slave Mode Operation ........................................................... 6-11
Multimaster Operation .......................................................... 6-12
SPI Data Transfer Operations ...................................................... 6-13
SPI Operation Using the Core ............................................... 6-13
SPI Operation Using DMA .................................................... 6-14
Master Mode DMA Operation .......................................... 6-15
Slave Mode DMA Operation ............................................. 6-19
Changing SPI Configuration ............................................. 6-21
Switching From Transmit To Receive DMA ....................... 6-23
Switching From Receive to Transmit DMA ........................ 6-24
To Next Page
Loading...
