Analog Devices SHARC ADSP-21368 - Page 12

Contents
xii ADSP-21368 SHARC Processor Hardware Reference
Active Low Versus Active High Frame Syncs .......................... 5-39
Sampling Edge for Data and Frame Syncs .............................. 5-39
Early Versus Late Frame Syncs ............................................... 5-40
Data-Independent Frame Syncs ............................................. 5-41
Frame Sync Error Detection .................................................. 5-42
Data Word Formats .................................................................... 5-43
Word Length ........................................................................ 5-43
Endian Format ...................................................................... 5-45
Data Packing and Unpacking ................................................ 5-45
Data Type ........................................................................ 5-46
Companding .................................................................... 5-47
SPORT Control Registers and Data Buffers ................................ 5-49
Register Writes and Effect Latency ......................................... 5-58
Serial Port Control Registers (SPCTLx) ................................. 5-59
Transmit and Receive Data Buffers
(TXSPxA/B, RXSPxA/B) .................................................... 5-67
Clock and Frame Sync Frequency Registers (DIVx) ................ 5-69
SPORT Reset ........................................................................ 5-71
SPORT Interrupts ................................................................ 5-72
Moving Data Between SPORTs and Internal Memory ................. 5-73
DMA Block Transfers ............................................................ 5-73
Setting Up DMA on SPORT Channels ............................. 5-75
SPORT DMA Parameter Registers ......................................... 5-76
SPORT DMA Chaining ................................................... 5-81
Single Word Transfers ........................................................... 5-81