ADSP-21368 SHARC Processor Hardware Reference xi
Contents
Left-Justified Sample Pair Mode Control Bits ..................... 5-17
Setting Word Length (SLEN) ............................................ 5-17
Enabling SPORT Master Mode (MSTR) ........................... 5-18
Selecting Transmit and Receive Channel Order (FRFS) ...... 5-18
Selecting Frame Sync Options (DIFS) ............................... 5-18
Enabling SPORT DMA (SDEN) ....................................... 5-19
I2S Mode .............................................................................. 5-20
Setting the Internal Serial Clock and Frame Sync Rates ...... 5-21
I2S Mode Control Bits ...................................................... 5-21
Setting Word Length (SLEN) ............................................ 5-22
Enabling SPORT Master Mode (MSTR) ........................... 5-23
Selecting Transmit and Receive Channel Order (FRFS) ...... 5-23
Selecting Frame Sync Options (DIFS) ............................... 5-23
Enabling SPORT DMA (SDEN) ....................................... 5-24
Multichannel Operation ........................................................ 5-25
Frame Syncs in Multichannel Mode ................................... 5-28
Multichannel Mode Control Bits ....................................... 5-29
Packed I2S Mode ................................................................... 5-33
Programming Packed I2S Mode ......................................... 5-34
SPORT Loopback ................................................................. 5-35
Clock Signal Options .................................................................. 5-36
Frame Sync Options .................................................................... 5-37
Framed Versus Unframed Frame Syncs ................................... 5-37
Internal Versus External Frame Syncs ..................................... 5-38
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