Analog Devices SHARC ADSP-21368

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Making Connections in the SRUs

4-42 ADSP-21368 SHARC Processor Hardware Reference

0111111 (0x3F) SRC2_DAT_OP_O SRC2 data output

1000000 (0x40) SRC3_DAT_OP_O SRC3 data output

1000001 (0x41) DIR_DAT_O SPDIF_RX data output

1000010 (0x42) DIR_FS_O SPDIF_RX frame sync output

1000011 (0x43) DIR_CLK_O SPDIF_RX clock output

1000100 (0x44) DIR_TDMCLK_O SPDIF_RX TDM clock output

1000101 (0x45) DIT_DAT_O SPDIF_TX data output

1000110 (0x46) SPORT0_TDV_O SPORT0 transmit data valid output

1000111 (0x47) SPORT1_TDV_O SPORT0 transmit data valid output

1001000 (0x48) SPORT2_TDV_O SPORT0 transmit data valid output

1001001 (0x49) SPORT3_TDV_O SPORT0 transmit data valid output

1001010 (0x4A) SPORT4_TDV_O SPORT0 transmit data valid output

1001011 (0x4B) SPORT5_TDV_O SPORT0 transmit data valid output

1001100 (0x4C) SPORT6_TDV_O SPORT0 transmit data valid output

1001101 (0x4D) SPORT7_TDV_O SPORT0 transmit data valid output

1001110 (0x4E) DIR_LRCLK_FB External PLL – feedback point connection

1001111 (0x4F) DIR_LRCLK_REF External PLL – reference point connection

1010000 (0x50) PCG_CLKC_O Select precision clock C

1011001 (0x51) PCG_CLKD_O Select precision clock D

1011010 (0x52) PCG_FSC_O Select precision frame sync C

1010011 (0x53) PCG_FSD_O Select precision frame sync D

1010100 – 1111101 Reserved

1111110 (0x7E) LOGIC_LEVEL_LOW Logic level low (0)

1111111 (0x7F) LOGIC_LEVEL_HIGH Logic level high (1)

Table 4-7. Group D Sources—Pin Signal Assignments (Cont’d)

Selection Code Source Signal Description (Source)

Analog Devices SHARC ADSP-21368 - Page 244