ADSP-21368 SHARC Processor Hardware Reference 5-85
Serial Ports
/* SPORT 5 Internal DMA memory address */
r0 = tx_buf5a; dm(IISP5A) = r0;
/* SPORT 5 Internal DMA memory access modifier */
r0 = 1; dm(IMSP5A) = r0;
/* SPORT 5 Number of DMA transfers to be done */
r0 = @tx_buf5a; dm(CSP5A) = r0;
/* SPORT 4 Internal DMA memory address */
r0 = rx_buf4a; dm(IISP4A) = r0;
/* SPORT 4 Internal DMA memory access modifier */
r0 = 1; dm(IMSP4A) = r0;
/* SPORT 4 Number of DMA5 transfers to be done */
r0 = @rx_buf4a; dm(CSP4A) = r0;
/* set internal loopback bit for SPORT4 & SPORT5 */
bit set ustat3 SPL;
dm(SPMCTL4) = ustat3;
/* Configure SPORT5 as a transmitter */
/* internally generating clock and frame sync */
/* CLKDIV = [fCCLK(333 MHz)/2 x FSCLK(8.325 MHz)] – 1 = 0x0004 */
/* FSDIV = [FSCLK(8.325 MHz)/TFS(.26 MHz)] – 1 = 31 = 0x001F */
R0 = 0x001F0004; dm(DIV5) = R0;
ustat4 = SPEN_A| /* Enable Channel A */
SLEN32| /* 32-bit word length */
FSR| /* Frame Sync Required */
SPTRAN| /* Transmit on enabled channels */
SDEN_A| /* Enable Channel A DMA */
IFS| /* Internally Generated Frame Sync */
ICLK; /* Internally Generated Clock */
dm(SPCTL5) = ustat4;
/* Configure SPORT4 as a receiver */
/* externally generating clock and frame sync */
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