ADSP-21368 SHARC Processor Hardware Reference 1-5
Introduction
Input Data Port (IDP). The IDP provides an additional input path to the
processor core, configurable as eight channels of serial data or seven chan-
nels of serial data and a single channel of up to 20-bit wide parallel data.
Two Serial Peripheral Interfaces (SPI). The primary SPI has dedicated
pins and the secondary is controlled through the DAI. The SPI provides
master or slave serial boot through the SPI, full-duplex operation, mas-
ter-slave mode, multimaster support, open drain outputs, programmable
baud rates, clock polarities, and phases.
Digital Audio Interface and Digital Peripheral Interface. The digital
audio interface (DAI) and the digital peripheral interface (DPI) are com-
prised of groups of peripherals and their signal routing units (SRU1 and
SRU2 respectively). This allows peripherals to be interconnected to suit a
wide variety of systems. It also allows the processors to include an arbi-
trary number and variety of peripherals while retaining high levels of
compatibility without increasing pin count.
Signal Routing Units (SRU1/SRU2). The SRUs provide configuration
flexibility by allowing software-programmable connections to be made
between the DAI/DPI components and the 20 DAI pins and 14 DPI pins.
I/O Processor (IOP). The IOP manages the SHARC processor’s off-chip
data I/O to alleviate the core of this burden. This unit manages the other
processor peripherals such as the SPI, DAI, and IDP as well as direct
memory accesses (DMA).
Table 1-1. SHARC Processor Features
Feature ADSP-21367 ADSP-21368 ADSP-21369 ADSP-21371 ADSP-21375
RAM 2M bit2M bit2M bit1M bit0.5M bit
ROM 6M bit
6M bit
1
6M bit
1
4M bit
1
2M bit
1
Audio Decoders
in ROM
2
Yes NoNoNoNo
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