Design Advantages
1-4 ADSP-21368 SHARC Processor Hardware Reference
Unconstrained Data Flow. The ADSP-21367/8/9 and ADSP-2137x pro-
cessors have a Super Harvard Architecture combined with a ten-port data
register file. In every cycle, the processor can write or read two operands to
or from the register file, supply two operands to the ALU, supply two
operands to the multiplier, and receive three results from the ALU and
multiplier. The processor’s 48-bit orthogonal instruction word supports
parallel data transfers and arithmetic operations in the same instruction.
40-Bit Extended Precision. The processor handles 32-bit IEEE float-
ing-point format, 32-bit integer and fractional formats (twos-complement
and unsigned), and extended-precision, 40-bit floating-point format. The
processors carry extended precision throughout their computation units,
limiting intermediate data truncation errors (up to 80 bits of precision are
maintained during multiply-accumulate operations).
Dual Address Generators. The processor has two data address generators
(DAGs) that provide immediate or indirect (pre- and post-modify)
addressing. Modulus, bit-reverse, and broadcast operations are supported
with no constraints on data buffer placement.
Efficient Program Sequencing. In addition to zero-overhead loops, the
processor supports single-cycle setup and exit for loops. Loops are both
nestable (six levels in hardware) and interruptable. The processors support
both delayed and non-delayed branches.
The ADSP-21367/8/9 and ADSP-2137x processors also provide the fol-
lowing features which increase the variety processor applications.
High Bandwidth I/O. The processors contain a dedicated, 6M bits
on-chip ROM, an external port, an SPI port, serial ports, digital audio
interface (DAI), and JTAG. The DAI incorporates a precision clock gen-
erator, input data port, and a signal routing unit.
Serial Ports. Provides an inexpensive interface to a wide variety of digital
and mixed-signal peripheral devices. The serial ports can operate at up to
half the processor core clock (
CCLK) rate.
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