ADSP-21368 SHARC Processor Hardware Reference v
Contents
Port, Buffer, and DMA Control Registers ............................... 2-26
Addressing ............................................................................ 2-29
External Port DMA ..................................................................... 2-35
Setting Up and Starting Chained DMA .................................. 2-36
Delay Line DMA ................................................................... 2-38
Serial Port DMA ......................................................................... 2-40
Setting Up and Starting Chained DMA .................................. 2-40
Inserting a TCB in an Active Chain ....................................... 2-41
Serial Peripheral Interface DMA .................................................. 2-42
Setting Up and Starting Chained DMA over the SPI .............. 2-42
UART DMA ............................................................................... 2-44
Notes On Using DMA With the UART ................................. 2-47
Memory-to-Memory DMA ......................................................... 2-48
Summary .................................................................................... 2-48
Programming Example ................................................................ 2-49
EXTERNAL PORT
External Memory Interface ............................................................ 3-2
External Memory Interface on the ADSP-2137x Processors ...... 3-3
Direct Execution of Instructions From External Memory ..... 3-3
Throughput and Instruction Execution Rate ........................ 3-3
Location of Interrupt Vector Table (IVT) ............................ 3-4
Instruction Cache ............................................................... 3-5
Instruction Storage and Packing .......................................... 3-9
Register Configurations for External Memory Execution .... 3-15
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