Contents
iv ADSP-21368 SHARC Processor Hardware Reference
Processor Peripherals ............................................................... 1-7
I/O Processor ..................................................................... 1-7
Digital Audio Interface (DAI) ............................................. 1-9
Digital Peripheral Interface (DPI) ..................................... 1-10
Development Tools ..................................................................... 1-10
Differences From Previous Processors .......................................... 1-11
I/O Architecture Enhancements ............................................ 1-11
Instruction Set Enhancements ............................................... 1-12
I/O PROCESSOR
General Procedure for Configuring DMA ...................................... 2-2
Core Access to IOP Registers ........................................................ 2-3
Configuring IOP/Core Interaction ................................................ 2-6
Interrupt-Driven I/O .............................................................. 2-6
Interrupt Latency in Interrupt-Driven Transfers ................ 2-11
Polling/Status-Driven I/O ..................................................... 2-12
DMA Controller Operation .................................................. 2-13
Chaining DMA Processes .................................................. 2-14
Transfer Control Block Chain Loading (TCB) ................... 2-16
Setting Up DMA Channel Allocation and Priorities ............... 2-18
Managing DMA Channel Priority ..................................... 2-19
DMA Bus Arbitration ....................................................... 2-20
Setting Up DMA Parameter Registers .......................................... 2-24
DMA Transfer Direction ....................................................... 2-24
Data Buffer Registers ............................................................ 2-25
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