ADSP-21368 SHARC Processor Hardware Reference A-25
Register Reference
29–27 SDRAW Row Address Width.
000=8, 001=9
010=10, 011=11
100=12, 101=13
110=14, 111=15
30 PGSZ 128 Program the SDRAM Controller for Page Size of 128 Words.
This bit allows programs to configure the SDC for a page size of
128 words (7 bits) which supports most available 32 Mb
SDRAMs.
1 = Page size 128 words. Column width = 7 bits, override CAW
settings.
0 = No effect, page size decided by SDCAW bits.
(Valid for ADSP-2137x processors only).
31 NO BSTOP No Burst Mode. This bit is used to select between full page burst
or no burst mode (BL=1). If set (=1), no burst mode is active and
the burst stop command is ignored. If cleared, full page burst is
active using the burst stop command for access interruption. This
bit must be cleared if the SDRAM does not support no burst
mode but supports full page burst.
(Valid for ADSP-2137x processors only).
Table A-6. SDRAM Control Register Bit Descriptions (Cont’d)
Bit Name Description
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