Two Wire Interface Registers
A-148 ADSP-21368 SHARC Processor Hardware Reference
Table A-61. Interrupt Source Register Bit Descriptions
Bit Name Description
0 TWISINIT Slave Transfer Initiated.
0 = A transfer is not in progress. An address match has not occurred
since the last time this bit was cleared.
1 = The slave has detected an address match and a transfer has been
initiated. This bit is sticky and is cleared by writing 1 to its bit loca-
tion.
1 TWISCOMP Slave Transfer Complete.
0 = The completion of a transfer not detected
1 = The transfer is complete and either a stop, or a restart was
detected. This bit is sticky and is cleared by writing a one to its bit
location
2 TWISERR Slave Transfer Error.
0 = No errors detected.
1 = An error has occurred. A restart or stop condition has occurred
during the data receive phase of a transfer. This bit is sticky and is
cleared by writing a one to its bit location.
3TWISOVF Slave Over Flow.
0 = No overflow detected.
1 = The slave transfer complete (TWISCOMP) was set at the time a
subsequent transfer has acknowledged an address phase. The trans-
fer continues, however, it may be difficult to delineate data of one
transfer from another. This bit is sticky and is cleared by writing a
one to its bit location.
4TWIMCOM Master Transfer Complete.
0 = The completion of a transfer not detected.
1 = The initiated master transfer is complete. In the absence of a
repeat start, the bus is released. This bit is sticky and is cleared by
writing a 1 to its bit location.
5TWIMERR Master Transfer Error.
0 = No errors detected.
1 = A master error occurred. The conditions surrounding the error
are indicated by the master status register (TWIMSTAT). This bit is
sticky and is cleared by writing a 1 to its bit location.
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