ADSP-21368 SHARC Processor Hardware Reference A-149
Register Reference
6 TWITXINT Transmit FIFO Service.
0 = No errors detected.
1 = The transmit FIFO buffer has one or two 8-bit locations avail-
able to be written. If TWITXINT2 is 0, this bit is set each time
TWITXS is updated to either 01 or 00. If TWITXINT2 is 1, this
bit is set each time TWITXS is updated to 00. This bit is sticky and
is cleared by writing 1 to its bit location.
7TWIRXINT Receive FIFO Service.
0 = No errors detected.
1 = The receive FIFO buffer has one or two 8-bit locations contain-
ing data to be read. If TWIRXINT2 is 0, this bit is set each time
TWIRXS is updated to either 01 or 11. If RTWIRXINT2 is 1, this
bit is set each time TWIRXS is updated to 11. This bit is sticky and
is cleared by writing 1 to its bit location.
Table A-61. Interrupt Source Register Bit Descriptions (Cont’d)
Bit Name Description