SDRAM Controller
3-76 ADSP-21368 SHARC Processor Hardware Reference
example, if
SDMODIFY = 1, then 32 locations in the boundary of the exter-
nal banks should not be used. These locations can be used without
optimization enabled. If SDMODIFY = 2 then 64 locations can not be used at
the boundaries of the external bank (if it is fully populated).
Achieving Maximum Throughput Using Core Accesses
Any break of sequential reads of 32 accesses can cause a throughput loss
due to a maximum of eight extra reads in 32-bit memories or four extra
reads (eight 16-bit reads). Listing 3-1 shows how to achieve maximum
throughput using core accesses. Any cycle between consecutive reads to an
SDRAM address results in nonsequential reads.
Listing 3-1. Maximum Throughput Using Sequential Reads
I0 = sdram_addr;
M0 = 1; /* SET sdmodify to 1 */
Lcntr = 1024, do(PC,1) until lce;
R0 = R0 + R1, R0 = dm (I0, M0);
The examples in Listing 3-2 show how read optimization can be used effi-
ciently using core accesses. In Listing 3-2, all reads are on the same page
and it takes 1184 cycles to perform 1024 reads.
Listing 3-2. Sequential Reads With Read Optimization
I0 = sdram_addr;
M0 = 2; /* SET sdmodify to 2 */
Lcntr = 1024, do(PC,1) until lce;
R0 = R0 + R1, R0 = dm (I0, M0);
In Listing 3-3, reads are not performed sequentially and the read optimi-
zation reduces throughput.
To Next Page
Loading...
Need help?
General
