Analog Devices SHARC ADSP-21368 - Page 331

ADSP-21368 SHARC Processor Hardware Reference 5-51
Serial Ports
CP0A Chain Pointer for DMA Chaining
Channel 0A
20 1 00C43
II0B Address for DMA Channel 0B 19 1 000C44
IM0B Internal Modifier for DMA Channel 0B 16 1 00C45
C0B Counter for DMA Channel 0B 16 1 00C46
CP0B Chain Pointer for DMA Chaining
Channel 0B
20 1 00C47
II1A Address for DMA Channel 1A 19 1 00C48
IM1A Internal Modifier for DMA Channel 1A 16 1 00C49
C1A Counter for DMA Channel 1A 16 1 00C4A
CP1A Chain Pointer for DMA Chaining
Channel 1A
20 1 00C4B
II1B Address for DMA Channel 1B 19 1 00C4C
IM1B Internal Modifier for DMA Channel 1B 16 1 00C4D
C1B Counter for DMA Channel 1B 16 1 00C4E
CP1B Chain Pointer for DMA Chaining
Channel 1B
20 1 00C4F
Reserved 00C50–00C5F
TX0A Transmitter FIFO Register in SP0A 32 1 00C60
RX0A Receiver FIFO Register in SP0A 32 1 00C61
TX0B Transmitter FIFO Register in SP0B 32 1 00C62
RX0B Receiver FIFO Register in SP0B 32 1 00C63
TX1A Transmitter FIFO Register in SP1A 32 1 00C64
RX1A Receiver FIFO Register in SP1A 32 1 00C65
Table 5-5. SPORT0 and SPORT1 Registers (Cont’d)
Register
Name
Function Width No. of
Registers
Memory Map
[17:0]