Analog Devices SHARC ADSP-21368

SPORT Control Registers and Data Buffers
5-52 ADSP-21368 SHARC Processor Hardware Reference
TX1B Transmitter FIFO Register in SP1B 32 1 00C66
RX1B Receiver FIFO Register in SP1B 32 1 00C67
Table 5-6. SPORT2 and SPORT3 Registers
Register
Name
Function Width No. of
Registers
Memory Map
[17:0]
SPCTL2–3 SPORT Control Register for SPORT2, 3 32 2 00400–00401
DIV2–3 Clock and Frame Sync Divisors for
SPORT2, SPORT3
32 2 00402–00403
SPMCTL2 SPORT Multichannel Control Register
for SPORT2
32 1 00404
SP2CS0–3 Multichannel Active channels select for
SPORT2
32 4 00405–00408
SP3CS0–3 Multichannel Active channels select for
SPORT3
32 4 00409–0040C
SP2CCS0–3 Multichannel Transmit Compand Select
(128 channels) for SPORT2
32 4 0040D–00410
SP3CCS0–3 Multichannel Receive Compand Select
(128 channels) for SPORT3
32 4 00411–00414
SPCNT2–3 Clock and Frame Sync; Divider Counter
(Internal Use Only) for SPORT2,
SPORT3
32 2 00415–00416
SPMCTL3 SPORT Multichannel Control Register
for SPORT3
32 1 00417
SPERRCT2–3 SPORT Error Interrupt Control Register
for SPORT2, SPORT3
7 2 00418–00419
Reserved 0041A–0043F
II2A Address for DMA Channel 2A 19 1 00440
Table 5-5. SPORT0 and SPORT1 Registers (Cont’d)
Register
Name
Function Width No. of
Registers
Memory Map
[17:0]