Analog Devices SHARC ADSP-21368

SPORT Control Registers and Data Buffers
5-54 ADSP-21368 SHARC Processor Hardware Reference
RX3A Receiver FIFO Register in SP3A 32 1 00465
TX3B Transmitter FIFO Register in SP3B 32 1 00466
RX3B Receiver FIFO Register in SP3B 32 1 00467
Table 5-7. SPORT4 and SPORT5 Registers
Register
Name
Function Width No. of
Registers
Memory Map
[17:0]
SPCTL4–5 SPORT Control Register for SPORT4, 5 32 2 00800–00801
DIV4–5 Clock and Frame Sync Divisors for
SPORT4, SPORT5
32 2 00802–00803
SPMCTL4 SPORT Multichannel Control Register
for SPORT4
32 1 00804
SP4CS0–3 Multichannel Active channels select for
SPORT4
32 4 00805–00808
SP5CS0–3 Multichannel Active channels select for
SPORT5
32 4 00809–0080C
SP4CCS0–3 Multichannel Transmit Compand Select
(128 channels) for SPORT4
32 4 0080D–00810
SP5CCS0–3 Multichannel Receive Compand Select
(128 channels) for SPORT5
32 4 00811–00814
SPCNT4–5 Clock and Frame Sync. Divider Counter
(Internal Use Only) for SPORT4,
SPORT5
32 2 00815–00816
SPMCTL5 SPORT Multichannel Control Register
for SPORT5
32 1 00817
SPERRCTL
4–5
SPORT Error Interrupt Control Register
for SPORT4, SPORT5
7 2 00818–00819
Reserved 0081A–0083F
Table 5-6. SPORT2 and SPORT3 Registers (Cont’d)
Register
Name
Function Width No. of
Registers
Memory Map
[17:0]