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Moving Data Between SPORTs and Internal Memory

5-78 ADSP-21368 SHARC Processor Hardware Reference

IMSP1A 0xC49 2 RXSP1A or TXSP1A

CSP1A 0xC4A 2 RXSP1A or TXSP1A

CPSP1A 0xC4B 2 RXSP1A or TXSP1A

IISP1B 0xC4C 3 RXSP1B or TXSP1B

IMSP1B 0xC4D 3 RXSP1B or TXSP1B

CSP1B 0xC4E 3 RXSP1B or TXSP1B

CPSP1B 0xC4F 3 RXSP1B or TXSP1B

Reserved

IISP2A 0x440 4 RXSP2A or TXSP2A

IMSP2A 0x441 4 RXSP2A or TXSP2A

CSP2A 0x442 4 RXSP2A or TXSP2A

CPSP2A 0x443 4 RXSP2A or TXSP2A

IISP2B 0x444 5 RXSP2B or TXSP2B

IMSP2B 0x445 5 RXSP2B or TXSP2B

CSP2B 0x446 5 RXSP2B or TXSP2B

CPSP2B 0x447 5 RXSP2B or TXSP2B

IISP3A 0x448 6 RXSP3A or TXSP3A

IMSP3A 0x449 6 RXSP3A or TXSP3A

CSP3A 0x44A 6 RXSP3A or TXSP3A

CPSP3A 0x44B 6 RXSP3A or TXSP3A

IISP3B 0x44C 7 RXSP3B or TXSP3B

IMSP3B 0x44D 7 RXSP3B or TXSP3B

CSP3B 0x44E 7 RXSP3B or TXSP3B

CPSP3B 0x44F 7 RXSP3B or TXSP3B

Table 5-13. SPORT DMA Parameter Registers Addresses (Cont’d)

Table of Contents3
Preface31
Purpose of this Manual31
Intended Audience31
Manual Contents32
What's New in this Manual34
Technical or Customer Support35
Supported Processors36
Product Information36
Myanalog.com37
Processor Product Information37
Related Documents38
Online Technical Documentation39
Printed Manuals41
Conventions43
Introduction45
Design Advantages45
Architectural Overview50
Processor Core51
Processor Peripherals51
I/O Processor51
Digital Audio Interface (DAI)53
Digital Peripheral Interface (DPI)54
Development Tools54
Differences from Previous Processors55
I/O Architecture Enhancements55
Instruction Set Enhancements56
General Procedure for Configuring DMA58
Core Access to IOP Registers59
Configuring Iop/Core Interaction62
Interrupt-Driven I/O62
Interrupt Latency in Interrupt-Driven Transfers67
Polling/Status-Driven I/O68
DMA Controller Operation69
Chaining DMA Processes70
Transfer Control Block Chain Loading (TCB)72
Setting up DMA Channel Allocation and Priorities74
Managing DMA Channel Priority75
DMA Bus Arbitration76
Setting up DMA Parameter Registers80
DMA Transfer Direction80
Data Buffer Registers81
Port, Buffer, and DMA Control Registers82
Addressing85
External Port DMA91
Setting up and Starting Chained DMA92
Delay Line DMA94
Serial Port DMA96
Setting up and Starting Chained DMA96
Inserting a TCB in an Active Chain97
Serial Peripheral Interface DMA98
Setting up and Starting Chained DMA over the SPI98
Uart Dma100
Notes on Using DMA with the UART103
Memory-To-Memory DMA104
Summary104
Programming Example105
External Port109
External Memory Interface110
External Memory Interface on the ADSP-2137X Processors111
Direct Execution of Instructions from External Memory111
Throughput and Instruction Execution Rate111
Location of Interrupt Vector Table (IVT)112
Instruction Cache113
Instruction Storage and Packing117
Register Configurations for External Memory Execution123
EMI Registers and Signals124
External Port Arbitration Logic126
Channel Freezing126
Managing Data Paths126
External Memory Interface Pins127
Asynchronous Memory Interface128
AMI Timing Control129
Wait States129
Bus Idle Cycles130
Bus Hold Cycles131
Setting AMI Modes132
External Memory Reads133
Data Packing133
External Memory Writes134
Data Packing135
Read/Write Throughput136
External Access Addressing136
External Port DMA138
Booting through the AMI138
SDRAM Controller138
Definition of Terms139
Timing External Memory Accesses144
Parallel Connection of Sdrams147
SDRAM Control Register (SDCTL)147
SDRAM Control Status Register (SDSTAT)157
SDRAM Refresh Rate Control Register (SDRRC)157
SDRAM Initialization159
SDRAM Address Mapping159
SDRAM Controller Address Mapping166
SDC Operation166
Single Bank Operation168
Multibank Operation (ADSP-2137X Processors)168
Data Mask (DQM)169
SDC Configuration169
SDC Commands171
Load Mode Register172
Single Bank Activation173
Multibank Activation (ADSP-2137X Processors)174
Single Precharge (ADSP-2137X Processors)174
Precharge All174
Read/Write175
Read/Write (ADSP-2137X Processors)177
Burst Stop (ADSP-2137X Processors)177
Auto-Refresh178
Self-Refresh Mode178
No Operation/Command Inhibit179
Changing System Clock During Runtime181
SDRAM Timing182
SDRAM Read Optimization183
External Memory Access Restrictions186
Shared Memory Interface187
Shared Memory Bus Arbitration187
Bus Arbitration Protocol190
Bus Arbitration Priority (RPBA)194
Bus Mastership Time-Out195
Bus Synchronization after Reset196
Bus Synchronization Notes199
Bus Lock and Semaphores200
Shared Memory Interface Status201
Shared Memory and the SDRAM Controller202
Shared Memory Booting202
Digital Audio/Digital Peripheral Interfaces203
Structure of the Interfaces204
DAI/DPI System Design205
Signal Routing Units210
Connecting Peripherals210
Pin Interface212
Pin Buffers as Signal Output Pins213
Pin Buffers as Signal Input Pins214
Bidirectional Pin Buffers215
Making Connections in the Srus217
DAI/SRU1 Connection Groups220
Group a Connections-Clock Signals221
Group B Connections-Data Signals227
Group C Connections-Frame Sync Signals233
Group D Connections-Pin Signal Assignments238
Group E Connections-Interrupts and Miscellaneous Signals245
Group F-Pin Enable Signals249
DPI/SRU2 Connection Groups253
Group a Connections-Input Routing Signals254
Group B Connections-Pin Assignment Signals258
Group C Connections-Pin Enable Signals262
DAI GPIO and Flags266
DPI GPIO and Flags267
Miscellaneous Signals267
DAI/DPI Interrupt Controller267
Relationship to the Core267
DAI Interrupts268
DPI Interrupts269
High and Low Priority Latches271
Rising and Falling Edge Masks272
Configuring the SPI274
Choosing the Pin Enable for the SPI Clock274
Configuring the Two Wire Interface275
Using the SRU() Macro to Configure the DAI278
Serial Ports281
Features282
Operation Modes283
Serial Port Signals285
Serial Port Signal Sensitivity289
SPORT Operation Modes290
Standard DSP Serial Mode291
Standard DSP Serial Mode Control Bits293
Clocking Options293
Frame Sync Options293
Data Formatting294
Data Transfers295
Status Information295
Left-Justified Sample Pair Mode296
Setting the Internal Serial Clock and Frame Sync Rates297
Left-Justified Sample Pair Mode Control Bits297
Setting Word Length (SLEN)297
Enabling SPORT Master Mode (MSTR)298
Selecting Transmit and Receive Channel Order (FRFS)298
Selecting Frame Sync Options (DIFS)298
Enabling SPORT DMA (SDEN)299
I2S Mode300
Setting the Internal Serial Clock and Frame Sync Rates301
I2S Mode Control Bits301
Setting Word Length (SLEN)302
Enabling SPORT Master Mode (MSTR)303
Selecting Transmit and Receive Channel Order (FRFS)303
Selecting Frame Sync Options (DIFS)303
Enabling SPORT DMA (SDEN)304
Multichannel Operation305
Frame Syncs in Multichannel Mode308
Multichannel Mode Control Bits309
Packed I2S Mode313
SPORT Loopback315
Clock Signal Options316
Frame Sync Options317
Framed Versus Unframed Frame Syncs317
Internal Versus External Frame Syncs318
Active Low Versus Active High Frame Syncs319
Sampling Edge for Data and Frame Syncs319
Early Versus Late Frame Syncs320
Data-Independent Frame Syncs321
Frame Sync Error Detection322
Data Word Formats323
Word Length323
Endian Format325
Data Packing and Unpacking325
Data Type326
Companding327
SPORT Control Registers and Data Buffers329
Serial Port Control Registers (Spctlx)339
Transmit and Receive Data Buffers (Txspxa/B, Rxspxa/B)347
Clock and Frame Sync Frequency Registers (DIVX)349
SPORT Reset351
SPORT Interrupts352
Moving Data between Sports and Internal Memory353
DMA Block Transfers353
Setting up DMA on SPORT Channels355
SPORT DMA Parameter Registers356
SPORT DMA Chaining361
Single Word Transfers361
SPORT Programming Examples362
Serial Peripheral Interface Ports373
Functional Description374
SPI Interface Signals376
SPI Clock Signal (SPICLK)376
SPICLK Timing377
SPI Flag Signals (SPIFLG3-0)378
Master out Slave in (MOSI)379
Master in Slave out (MISO)379
SPI General Operations380
SPI Enable381
Open Drain Mode (OPD)381
Master Mode Operation382
Slave Mode Operation383
Multimaster Operation384
SPI Data Transfer Operations385
SPI Operation Using the Core385
SPI Operation Using DMA386
Master Mode DMA Operation387
Slave Mode DMA Operation391
Changing SPI Configuration393
Switching from Transmit to Receive DMA395
Switching from Receive to Transmit DMA396
DMA Error Interrupts397
DMA Chaining399
SPI Transfer Formats399
Beginning and Ending an SPI Transfer401
SPI Word Lengths403
16-Bit Word Lengths404
Packing404
SPI Interrupts405
Error Signals and Flags407
Mode Fault Error (MME)407
Transmission Error Bit (TUNF)409
Reception Error Bit (ROVF)409
Transmit Collision Error Bit (TXCOL)409
Programming Notes410
Routing SPI Signals Using the DPI410
Programming Examples410
Input Data Port419
Serial Inputs421
Parallel Data Acquisition Port (PDAP)421
Masking427
Packing Mode 11428
Packing Mode 10429
Packing Mode 01429
Packing Mode 00430
Clocking Edge Selection430
Hold Input430
PDAP Strobe432
FIFO Control and Status433
FIFO to Memory Data Transfer434
IDP Transfers Using the Core435
Starting an Interrupt-Driven Transfer436
IDP Transfers Using DMA438
Simple DMA438
Ping-Pong DMA440
DMA Transfer Notes443
DMA Channel Parameter Registers445
IDP (DAI) Interrupt Service Routines for Dmas446
FIFO Overflow448
Input Data Port Programming Example449
Pulse Width Modulation453
PWM Implementation453
Edge-Aligned Mode454
Center-Aligned Mode455
Switching Frequencies457
Dead Time458
Duty Cycles459
Duty Cycles and Dead Time460
Over Modulation464
Update Modes467
Single Update467
Configurable Polarity467
PWM Pins and Signals468
Crossover468
PWM Accuracy469
PWM Registers470
Duty Cycles471
Output Enable472
Programming Example473
AES3/SPDIF Stream Format478
Subframe Format479
Channel Coding481
Preambles482
S/PDIF Transmitter483
Channel Status485
SRU1 Signals for the S/PDIF Transmitter486
Modes of Operation488
Standalone Mode489
Structure of the Serial Input Data490
S/PDIF Receiver492
S/PDIF Receiver Registers493
SRU1 Receiver Signals494
Phase-Locked Loop495
Channel Status Decoding495
Compressed or Non-Linear Audio Data496
Emphasized Audio Data497
Single-Channel, Double-Sampling Frequency Mode497
Error Handling498
Interrupts500
DAI Programming Examples500
Control Register500
SRU1 Programming for Input and Output Streams501
Control Register Programming and Enable501
S/PDIF Receiver Programming Guidelines501
Control Register501
SRU1 Programming502
Control Register Programming502
Receiver Locking502
Status Bits502
Interrupted Data Streams on the Receiver503
Asynchronous Sample Rate Converter505
Theory of Operation506
Conceptual Model508
Hardware Model511
Sample Rate Converter Architecture512
Group Delay516
SRC Operation516
Enabling the SRC517
Serial Data Ports517
Data Format517
Time-Division Multiplex (TDM) Output Mode519
TDM Input Mode520
Matched-Phase Mode520
Bypass Mode522
De-Emphasis Filter522
Mute Control523
Soft Mute524
Hard Mute524
Auto Mute524
SRC Registers525
Programming the SRC Module526
SRC Control Register Programming526
SRU Programming526
SRC Mute-Out Interrupt527
Sample Rate Ratio527
Programming Summary527
11 Uart Port Controller529
Serial Communications530
UART Control and Status Registers531
Uartxlcr Registers531
Uartxlsr Register532
Uartxthr Register532
Uartxrbr Register533
Uartxier Register535
Uartxiir Register537
Uartxdll and Uartxdlh Registers539
Uartxscr Register540
Uartxmode Register541
I/O Mode541
Packing Mode543
Two Wire Interface Controller545
Overview545
Architecture546
Register Descriptions548
TWI Master Internal Time Register548
TWIDIV Register549
Slave Mode Control Register549
Slave Mode Address Register550
Slave Mode Status Register550
Master Mode Control Register550
Master Mode Address Register550
Master Mode Status Register551
FIFO Control Register551
FIFO Status Register551
Interrupt Source Register551
Interrupt Enable Register552
16-Bit Transmit FIFO Register552
8-Bit Receive FIFO Register553
16-Bit Receive FIFO Register554
Data Transfer Mechanics554
Clock Generation and Synchronization555
Bus Arbitration556
General Call Support558
Fast Mode558
Programming Examples559
General Setup559
Slave Mode559
Master Mode Clock Setup561
Master Mode Transmit561
Master Mode Receive562
Repeated Start Condition563
Transmit/Receive Repeated Start Sequence563
Receive/Transmit Repeated Start Sequence565
Electrical Specifications566
Precision Clock Generators567
Clock Outputs569
Frame Sync Outputs570
Normal Mode571
Bypass Mode572
Frame Sync Output Synchronization with an External Clock573
Frame Sync574
Phase Shift575
Phase Shift Settings576
Pulse Width576
Bypass Mode578
Bypass as a Pass through578
Bypass as a One-Shot579
Programming Examples580
PCG Setup for I2S or Left-Justified DAI580
Clock and Frame Sync Divisors PCG Channel B586
PCG Channel a and B Output Example589
14 System Design593
Processor Pin Descriptions594
Pin Multiplexing594
Choosing EP Data Mode598
Interrupt and Timer Pins600
Core-Based Flag Pins600
Programming Flags601
JTAG Interface Pins604
Clock Derivation605
Power Management Control Register606
PLL Programming Examples608
Phase-Locked Loop Startup611
RESET and CLKIN612
Running Reset (ADSP-2137X)614
System Design Considerations615
Running Reset Control Register (RUNRSTCTL)617
Programming the RUNRSTCTL Register618
Reset Generators619
Timing Specifications620
Input Synchronization Delay624
Conditioning Input Signals624
RESET Input Hysteresis625
Designing for High Frequency Operation625
Clock Specifications and Jitter625
Other Recommendations and Suggestions626
Decoupling Capacitors and Ground Planes627
Oscilloscope Probes627
Recommended Reading628
Booting629
External Port Booting631
Booting through the AMI631
Shared Memory Booting632
SPI Port Booting634
32-Bit SPI Host Boot635
16-Bit SPI Host Boot636
8-Bit SPI Host Boot638
Slave Boot Mode639
Master Boot640
Booting from an SPI Flash643
Booting from an SPI PROM (16-Bit Address)644
Booting from an SPI Host Processor644
Data Delays, Latencies, and Throughput644
Execution Stalls645
DAG Stalls646
Memory Stalls646
IOP Register Stalls647
DMA Stalls648
IOP Buffer Stalls648
Register Reference649
I/O Processor Registers650
Notes on Reading Register Drawings651
System Control Register (SYSCTL653
System Status Register (SYSTAT657
External Port Registers658
External Port Control Register (EPCTL658
External Port DMA Control Registers (Dmacx662
AMI Control Registers (Amictlx665
AMI Status Register (AMISTAT668
SDRAM Control Register (SDCTL669
SDRAM Control Status Register (SDSTAT674
SDRAM Refresh Rate Control Register (SDRRC674
Memory-To-Memory DMA Register676
Serial Port Registers677
SPORT Serial Control Registers (Spctlx677
SPORT Multichannel Control Registers (Spmctlx688
SPORT Transmit Buffer Registers (Txspx691
SPORT Receive Buffer Registers (Rxspx692
SPORT Divisor Registers (DIVX692
SPORT Count Registers (Spcntx693
SPORT Active Channel Select Registers (Spxcsy694
SPORT Compand Registers (Spxccsy695
SPORT Error Control Register (Sperrctlx696
SPORT Error Status Register (SPERRSTAT697
SPORT DMA Index Registers (Iispx698
SPORT DMA Modifier Registers (Imspx698
SPORT DMA Count Registers (Cspx699
SPORT Chain Pointer Registers (Cpspx699
Serial Peripheral Interface Registers700
SPI Control Registers (SPICTL, SPICTLB700
SPI Port Status (SPISTAT, SPISTATB) Registers704
SPI Port Flags Registers (SPIFLG, SPIFLGB706
SPI Receive Buffer Registers (RXSPI, RXSPIB707
RXSPI Shadow Registers (RXSPI_SHADOW, RXSPIB_SHADOW707
SPI Baud Rate Registers (SPIBAUD, SPIBAUDB708
SPI DMA Registers709
SPI DMA Configuration Registers709
Spidmacb709
SPI DMA Start Address Registers (IISPI, IISPIB709
SPI DMA Address Modify Registers (IMSPI, IMSPIB709
SPI DMA Word Count Registers (CSPI, CSPIB709
SPI DMA Chain Pointer Registers (CPSPI, CPSPIB709
Input Data Port Registers713
Input Data Port Control Register 0 (IDP_CTL0714
Input Data Port Control Register 1 (IDP_CTL1716
Input Data Port FIFO Register (IDP_FIFO717
Input Data Port DMA Control Registers718
Idp_Dma_Ix718
Idp_Dma_Mx719
Idp_Dma_Cx719
Input Data Port Ping-Pong DMA Registers720
IDP Ping-Pong Index Registers (Idp_Dma_Ixa720
IDP Ping-Pong Count Registers (Idp_Dma_Pcx721
Parallel Data Acquisition Port Control Register (IDP_PP_CTL722
Pulse Width Modulation Registers726
PWM Global Status Register (PWMGSTAT727
PWM Control Register (Pwmctlx728
PWM Status Registers (Pwmstatx729
PWM Period Registers (Pwmperiodx729
PWM Output Disable Registers (Pwmsegx730
PWM Polarity Select Registers (Pwmpolx731
PWM Channel Duty Control Registers (Pwmax, Pwmbx732
PWM Channel Low Duty Control Registers (Pwmalx, Pwmblx732
PWM Dead Time Registers (Pwmdtx733
Sony/Philips Digital Interface Registers734
Transmitter Control Register (DITCTL734
Left Channel Status for Subframe a Registers (Ditchanax737
Right Channel Status for Subframe B Registers (Ditchanbx738
User Bits Buffer Registers for Subframe a Registers (Ditusrbitax738
User Bits Buffer Registers for Subframe B Registers (Ditusrbitbx739
Receiver Control Register (DIRCTL740
Receiver Status Register (DIRSTAT742
Left Channel Status for Subframe a Register (DIRCHANL744
Right Channel Status for Subframe B Register (DIRCHANR744
Sample Rate Converter Registers745
SRC Control Registers (Srcctlx745
SRC Mute Register (SRCMUTE755
SRC Ratio Registers (Srcratx756
DAI/DPI Registers757
Digital Audio Interface Status Register (DAI_STAT757
DAI Resistor Pull-Up Enable Register (DAI_PIN_PULLUP759
DAI Pin Buffer Status Register (DAI_PIN_STAT760
DAI Interrupt Controller Registers760
DPI Resistor Pull-Up Enable Register (DPI_PIN_PULLUP763
DPI Pin Buffer Status Register (DPI_PIN_STAT764
DPI Interrupt Controller Registers764
UART Control and Status Registers766
Line Control Registers (Uartxlcr766
Line Status Registers (Uartxlsr768
Transmit Hold Registers (Uartxthr769
Receive Buffer Registers (Uartxrbr770
Interrupt Enable Registers (Uartxier771
Interrupt Identification Registers (Uartxiir772
Divisor Latch Registers (Uartxdll, Uartxdlh773
Scratch Registers (Uartxscr774
Mode Registers (Uartxmode774
UART DMA Registers775
DMA Control Registers776
DMA Status Registers777
Two Wire Interface Registers778
Master Internal Time Register (TWIMITR779
Clock Divider Register (TWIDIV780
Slave Mode Control Register (TWISCTL781
Slave Address Register (TWISADDR783
Slave Status Register (TWISSTAT783
Master Control Register (TWIMCTL784
Master Address Register (TWIMADDR787
Master Status Register (TWIMSTAT788
FIFO Control Register (TWIFIFOCTL791
FIFO Status Register (TWIFIFOSTAT793
Interrupt Source Register (TWIIRPTL795
Interrupt Enable Register (TWIIMASK798
8-Bit Transmit FIFO Register (TXTWI8800
16-Bit Transmit FIFO Register (TXTWI16801
8-Bit Receive FIFO Register (RXTWI8802
16-Bit Receive FIFO Register (RXTWI16802
Precision Clock Generator Registers803
Control Registers (Pcg_Ctlxx803
PCG Pulse Width Registers806
PCG Frame Synchronization Registers (Pcg_Syncx808
Peripheral Interrupt Priority Control Registers812
Peripheral Interrupt Priority Control812
Registers (Picrx812
Peripheral Interrupt Priority0 Control Register (PICR0815
Peripheral Interrupt Priority1 Control Register (PICR1816
Peripheral Interrupt Priority2 Control Register (PICR2817
Peripheral Interrupt Priority3 Control818
Register (PICR3818
Power Management Control Register (PMCTL818
Hardware Breakpoint Control Register823
Enhanced Emulation Status Register827
Interrupt Vector Tables831
Interrupt Priorities834
Interrupt Registers836
Interrupt Register (LIRPTL836
Interrupt Latch Register (IRPTL843
Interrupt Mask Register (IMASK848
Interrupt Mask Pointer Register (IMASKP852
Index857

Brand	Analog Devices
Model	SHARC ADSP-21368
Category	Computer Hardware
Language	English

Analog Devices SHARC ADSP-21368 User Manual

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