ADSP-21368 SHARC Processor Hardware Reference 12-13
Two Wire Interface Controller
The TWI controller’s special-case start and stop conditions include:
• TWI controller addressed as a slave-receiver
If the master asserts a stop condition during the data phase of a
transfer, the TWI controller concludes the transfer (TWISCOMP).
Figure 12-6. TWI Bus Arbitration
Figure 12-7. TWI Start and Stop Conditions
START
SCL (BUS)
TWI CONTROLLER
DATA
SECOND MASTER
DATA
SDA (BUS)
ARBITRATION
LOST
START
SCL (BUS)
SDA (BUS)
STOP
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