Serial Port Registers
A-34 ADSP-21368 SHARC Processor Hardware Reference
Figure A-16. SPCTLx Register (Bits 15 – 0) for I
2
S and Left-Justified
Sample Pair Modes
SPCTL0 (0xC00) SPCTL1 (0xC01)
SPCTL2 (0x400) SPCTL3 (0x401)
SPCTL4 (0x800) SPCTL5 (0x801)
SPCTL6 (0x4800) SPCTL7 (0x4801)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
SPEN_A
DIFS
Data Independent Frame Sync
1=Data independent
0=Data dependent
Reserved
OP MODE
SPORT Operation Mode
1=I
2
S or left-justified sample pair mode,
this bit must be set to 1
MSTR
I
2
S Serial and L/R Clock Master2
1=Internal clock and word select
0=External clock and word select
SPORT Enable A
1=Enable
0=Disable
Reserved
SLEN
Serial word length=1
PACK
16/32 Packing
1=Packing
0=No packing
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