Analog Devices SHARC ADSP-21368 - Page 681

ADSP-21368 SHARC Processor Hardware Reference A-33
Register Reference
Figure A-15. SPCTLx Register (Bits 31–16) for I
2
S and Left-Justified
Sample Pair Modes
31 30 29 28 27 26
24
23 22 21 20 19 18 17 16
0000000000100000
DXS_A
Data Buffer Channel A Status
11=Full, 10=Partially Full, 00=Empty
FRFS
See Table 5-1 on page 5-11
DERR_A
Channel A Error Status (Sticky)
SPTRAN=1 Transmit underflow status
SPTRAN=0 Receive overflow status
SDEN_A
DMA Channel A Enable
1=Enable
0=Disable
DXS_B
Data Buffer Channel B Status
11=Full, 10=Partially Full, 00=Empty
DERR_B
Channel B Error Status (Sticky)
SPTRAN=1 Transmit underflow status
SPTRAN=0 Receive overflow status
SPTRAN
SPORT Transaction
1=Active transmit buffers TXSPXA/TXSPXB
0=Enable receive buffers RXSPXA/RXSPXB
SPEN_B
SPORT Enable B
1=Enable
0=Disable
BHD
Buffer Hang Disable
1=Ignore core hang
0=Core stall when TXSPx Full
or RXSPx empty
LAFS
Late Frame Sync
SCHEN_A
DMA Channel A Chaining Enable
1=Enable
0=Disable
SDEN_B
DMA Channel B Enable
1=Enable
0=Disable
SCHEN_B
DMA Channel B Chaining Enable
1=Enable
0=Disable
Reserved
25
SPCTL0 (0xC00) SPCTL1 (0xC01)
SPCTL2 (0x400) SPCTL3 (0x401)
SPCTL4 (0x800) SPCTL5 (0x801)
SPCTL6 (0x4800) SPCTL7 (0x4801)