Sample Rate Converter Registers
A-100 ADSP-21368 SHARC Processor Hardware Reference
13–12 SRC0_LENOUT Output Word Length Select. Selects the serial output
word length on SRC 0 as follows:
00 = 24 bits
01 = 20 bits
10 = 18 bits
11 = 16 bits
Any word length less than 24 bits will have dither added
to the unused LSBs if SRCx_DITHER is enabled (= 1).
14 SRC0_MPHASE Match-Phase Mode Select. Configures the SRC 0 mod-
ules to not use their own internally-generated sample rate
ratio but use an externally-generated ratio. Used with
TDM data.
0 = Matched-phase mode disabled (default)
1 = Matched-phase mode enabled
15 SRC0_ENABLE SRC0 Enable. Enables SRC 0.
0 = Disabled
1 = Enabled
16 SRC1_HARD_MUTE Hard Mute. Hard mutes SRC 1.
1 = Mute (default)
17 SRC1_AUTO_MUTE Auto Hard Mute. Auto hard mutes SRC 1 when one of
the non-audio bits is asserted by the SPDIF receiver. See
Table A-39 on page A-95.
0 = No mute
1 = Mute (default)
20–18 SRC1_SMODEIN Serial Input Format. Selects the serial input format for
SRC 1 as follows.
000 = Default, format is left-justified
001 = I
2
S
010 = TDM
100 = 24-bit right-justified
101 = 20-bit right-justified
110 = 18-bit right-justified
111 = 16-bit right-justified
21 SRC1_BYPASS Bypass Mode Enable. Output of SRC 1 is the same as
input.
Table A-42. SRCCTL0 Register Bit Descriptions (Cont’d)
Bit Name Description
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