ADSP-21368 SHARC Processor Hardware Reference A-99
Register Reference
4–2 SRC0_SMODEIN Serial Input Format. Selects the serial input format for
SRC 0 as follows.
000 = Default, format is left-justified
001 = I
2
S
010 = TDM
100 = 24-bit right-justified
101 = 20-bit right-justified
110 = 18-bit right-justified
111 = 16-bit right-justified
5 SRC0_BYPASS Bypass SRC0. Output of SRC 0 is the same as the input.
7–6 SRC0_DEEMPHASIS De-emphasis Filter Select. Enables de-emphasis on
incoming audio data for SRC 0.
00 = No Deemphasis
01 = 33 kHz
10 = 44.1 kHz
11 = 48 kHz
8 SRC0_SOFTMUTE Soft Mute. Enables soft mute on SRC 0.
0 = No mute
1 = Mute (default)
9 SRC0_DITHER Dither Select. Enables dithering on SRC 0 when a word
length less than 24 bits is selected.
0 = Dithering is disabled (default)
1 = Dithering is enabled
11–10 SRC0_SMODEOUT Serial Output Format. Selects the serial output format
on SRC 0, as follows:
00 = Left-justified (default)
01 = I
2
S
10 = TDM mode
11 = Right-justified
Table A-42. SRCCTL0 Register Bit Descriptions (Cont’d)
Bit Name Description
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