ADSP-21368 SHARC Processor Hardware Reference A-103
Register Reference
Figure A-39. SRCCTL1 Register (Bits 0–15)
Table A-43. SRCCTL1 Register Bit Descriptions
Bit Name Description
0 SRC2_HARD_MUTE Hard Mute. Hard mutes SRC 2.
1 = Mute (default)
1 SRC2_AUTO_MUTE Auto Hard Mute. Auto hard mutes SRC 2 when one of
the non-audio bits is asserted by the SPDIF receiver. See
Table A-39 on page A-95.
0 = No mute
1 = Mute (default)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
SRC2_HARD_MUTE
SRC2_RESET
SRC0, 2 Reset
1=SRC enabled
0=SRC disabled
SRC 2 Hard Mute Enable
1=Enabled
0=Disabled
SRC2_AUTO_MUTE
SRC 2 Auto Hard Mute
Enable (from SPDIF RX)
1=Enabled
0=Disabled
SRC2_BYPASS
SRC 2 Deemphasis Filter
1=Enabled
0=Disabled (default)
SRC 2 Bypass Mode
1=Bypass enabled
0=Bypass disabled
SRC2_DEEMPHASIS
SRC2_MPHASE
SRC 2 Matched-Phase Mode
1=Enabled
0=Disabled
SRC2_LENOUT
SRC 2 Output Word Length
00=24-bit, 01=20-bit
10=18-bit, 11=16-bit
SRC2_SMODEOUT
SRC 2 Serial Output Format
00=Left-justified (default)
01=I
2
S
10=TDM
11=Right-justified
SRC2_DITHER
SRC 2 Dither Enable
1=Enable
0=Disable
SRC 2 Soft Mute Enable
1=Mute (default)
0=No mute
SRC2_SOFTMUTE
SRC2_SMODEIN
SRC 2 Serial Input Format
000=Left-justified (default)
001=I
2
S
010=TDM
100=24-bit right-justified
101=20-bit right-justified
110=18-bit right-justified
111=16-bit right-justified
SRCCTL1 (0x2491)
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