Analog Devices SHARC ADSP-21368

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Sample Rate Converter Registers

A-102 ADSP-21368 SHARC Processor Hardware Reference

Figure A-38. SRCCTL1 Register (Bits 16–31)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0000000000000000

SRCCTL1 (0x2491)

SRC3_ENABLE

SRC 3 Enable

1=SRC enabled

0=SRC disabled

SRC3_MPHASE

SRC 3 Matched-Phase Mode

1=Enabled

0=Disabled

SRC3_LENOUT

SRC 3 Output Word Length

00=24-bit

01=20-bit

10=18-bit

11=16-bit

SRC3_SMODEOUT

SRC 3 Serial Output Format

00=Left-justified (default)

01=I

10=TDM

11=Right-justified

SRC3_DITHER

SRC 3 Dither Enable

1=Enable

0=Disable

SRC 3 Soft Mute Enable

1=Mute (default)

0=No mute

SRC3_SOFTMUTE

SRC3_HARD_MUTE

SRC 3 Hard Mute Enable

1=Enabled

0=Disabled

SRC3_AUTO_MUTE

SRC 3 Auto Hard Mute

Enable (from SPDIF RX)

1=Enabled

0=Disabled

SRC3_BYPASS

SRC 3 De-emphasis Filter

1=Enabled

0=Disabled (default)

SRC 3 Bypass Mode

1=Bypass enabled

0=Bypass disabled

SRC3_DEEMPHASIS

SRC3_SMODEIN

SRC 3 Serial Input Format

000=Left-justified (Default)

001=I

010=TDM

100=24-bit right-justified

101=20-bit right-justified

110=18-bit right-justified

111=16-bit right-justified

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