Sample Rate Converter Registers
A-104 ADSP-21368 SHARC Processor Hardware Reference
4–2 SRC2_SMODEIN Serial Input Format. Selects the serial input format for
SRC 2 as follows.
000 =Default, format is left-justified
001 = I
2
S
010 = TDM
100 = 24-bit right-justified
101 = 20-bit right-justified
110 = 18-bit right-justified
111 = 16-bit right-justified
5 SRC2_BYPASS Bypass SRCx. Output of SRC 2 is the same as input
7–6 SRC2_DEEMPHASIS De-emphasis Filter Select. Enables de-emphasis on
incoming audio data for SRC 2.
00 = No de-emphasis
01 = 33 kHz
10 = 44.1 kHz
11 = 48 kHz
8 SRC2_SOFTMUTE Soft Mute. Enables soft mute on SRC 2.
0 = No mute
1 = Mute (default)
9 SRC2_DITHER Dither Select. Enables dithering on SRC 2 when a word
length less than 24 bits is selected.
0 = Dithering is disabled (default)
1 = Dithering is enabled
11–10 SRC2_SMODEOUT Serial Output Format. Selects the serial output format
on SRC 2 as follows:
00 = Left-justified (default)
01 = I
2
S
10 = TDM mode
11 = Right-justified
Table A-43. SRCCTL1 Register Bit Descriptions (Cont’d)
Bit Name Description
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