Analog Devices SHARC ADSP-21368 - Page 799

ADSP-21368 SHARC Processor Hardware Reference A-151
Register Reference
Table A-62. Interrupt Mask Register Bit Descriptions
Bit Name Description
0 TWISINIT Slave Transfer Initiate Interrupt Enable.
0 = The corresponding interrupt source is prevented from
asserting the interrupt output.
1 = The corresponding interrupt source asserts the interrupt
output.
1 TWISCOMP Slave Transfer Complete Interrupt.
0 = The corresponding interrupt source is prevented from
asserting the interrupt output.
1 = The corresponding interrupt source asserts the interrupt
output.
2 TWISERR Slave Transfer Error Interrupt.
0 = The corresponding interrupt source is prevented from
asserting the interrupt output.
1 = The corresponding interrupt source asserts the interrupt
output.
3 TWISOVF Slave Over Flow Interrupt Enable.
0 = The corresponding interrupt source is prevented from
asserting the interrupt output.
1 = The corresponding interrupt source asserts the interrupt
output.
4 TWIMCOM Master Transfer Complete Interrupt Enable.
0 = The corresponding interrupt source is prevented from
asserting the interrupt output.
1 = The corresponding interrupt source asserts the interrupt
output.
5 TWIMERR Master Transfer Error Interrupt Enable.
0 = The corresponding interrupt source is prevented from
asserting the interrupt output.
1 = The corresponding interrupt source asserts the interrupt
output.