Interrupt Registers
B-20 ADSP-21368 SHARC Processor Hardware Reference
9IRQ1IIRQ1 Hardware Interrupt. Unmasks the IRQ1I interrupt (if set, = 1),
or masks the IRQ1I interrupt (if cleared, = 0). An IRQ1I occurs when
an external device asserts the FLAG1 pin configured as IRQ1.
10 IRQ0I IRQ0 Hardware Interrupt. Unmasks the IRQ0I interrupt (if set, = 1),
or masks the IRQ0
I interrupt (if cleared, = 0). An IRQ0I occurs when
an external device asserts the FLAG0 pin configured as IRQ0.
11 DAI1I DAI High Priority Interrupt. Unmasks the DAI1I interrupt
(if set, = 1), or masks the DAI1I interrupt (if cleared, = 0). This is the
higher priority option.
12 SPIAI SPI Transmit or Receive High Priority Interrupt. Unmasks the SPIAI
interrupt (if set, = 1), or masks the SPIAI interrupt (if cleared, = 0).
This is the higher priority option.
13 GPTMR0I General-Purpose IOP Timer 0 Interrupt. Unmasks the GPTMR0I
interrupt (if set, = 1), or masks the GPTMR0I interrupt
(if cleared, = 0).
14 SP1I SPORT 1 Interrupt. Unmasks the SP1I interrupt (if set, = 1), or masks
the SP1I interrupt (if cleared, = 0). An SP1I interrupt occurs two cycles
after the last bit of an input/output serial word is latched into/from
RXSP1A/TXSP1A, or RXSP1B/TXSP1B.
15 SP3I SPORT 3 Interrupt. Unmasks the SP3I interrupt (if set, = 1), or masks
the SP3I interrupt (if cleared, = 0). An SP3I interrupt occurs two cycles
after the last bit of an input/output serial word is latched into/from
RXSP3A/TXSP3A, or RXSP3B/TXSP3B.
16 SP5I SPORT 5 Interrupt. Unmasks the SP5I interrupt (if set, = 1), or masks
the SP5I interrupt (if cleared, = 0). An SP5I interrupt occurs two cycles
after the last bit of an input/output serial word is latched into/from
RXSP5A/TXSP5A, or RXSP5B/TXSP5B.
17 Reserved
18 P15I Programmable Interrupt 15 (MTMDMA Interrupt).
19 Reserved
Table B-6. IMASK Register Bit Descriptions (Cont’d)
Bit Name Description
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