Analog Devices SHARC ADSP-21368

External Memory Interface
3-12 ADSP-21368 SHARC Processor Hardware Reference
words and packs them to form the 48-bit instruction to be executed. The
address is automatically incremented, and program execution continues
with placing the next address on the external address bus, and so on.
In Table 3-3, the logical to physical translation is a multiplication by a
factor of 3/2 and N = 0x8AAAA9. Therefore, the 32-bit wide memory
supports 8.6 million instructions.
In Table 3-4 the logical to physical translation is a multiplication by a fac-
tor of 3 and N = 0x355554. Therefore, the 16-bit wide memory supports
3.3 million instructions.
Table 3-3. Logical Versus Physical Address Mapping, 32-Bit Asynchronous
Memory
Logical Address Dispatched
by Program Sequencer
Physical Address Observed
on the External Address Bus
Data
31 0
0x200000 0x300000 Instr0[31:0]
0x300001 Instr1[15:0] Instr0[47:32]
0x200001 0x300001 Instr1[47:16]
0x300002 Instr2[31:0]
0x200002 0x300002 Instr3[15:0] Instr2[47:32]
0x300003 Instr3[47:16]
... ...
...
... ...
...
0xAAAA9 0xFFFFFE InstrN[31:0]
0xFFFFFF 0000 InstrN[47:32]