ADSP-21368 SHARC Processor Hardware Reference 3-13
External Port
Table 3-5 and Table 3-6 show the logical to physical address translation
maps for external SDRAM. In SDRAM, there is an additional 2 bits of
address generation available to the SDRAM controller. Therefore, the
external addressable range is larger than with asynchronous memory and
the entire allowable internal address range of 24 bits can be accessed in
external memory.
In Table 3-5, N = 0xE00000. Therefore, the total number of external
memory instructions for a 32-bit wide SDRAM memory is 14 million.
Table 3-4. Logical Versus Physical Address Mapping, 16-Bit Asynchronous
Memory
Logical Address Dispatched
by Program Sequencer
Physical Address Observed
on the External Address Bus
Data
16 0
0x200000 0x600000 Instr0[15:0]
0x600001 Instr0[31:16]
0x600002 Instr0[47:32]
0x200001 0x600003 Instr1[15:0]
0x600004 Instr1[31:16]
0x600005 Instr1[47:32]
0x200002 0x600006 Instr2[15:0]
0x600007 Instr2[31:16]
0x600008 Instr2[47:32]
... ...
... ...
... ...
0x555554 0xFFFFFD InstrN[15:0]
0xFFFFFE InstrN[31:16]
0xFFFFFF InstrN[47:32]
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