Analog Devices SHARC ADSP-21368 - Page 16

Contents
xvi ADSP-21368 SHARC Processor Hardware Reference
Switching Frequencies ............................................................. 8-5
Dead Time ............................................................................. 8-6
Duty Cycles ............................................................................ 8-7
Duty Cycles and Dead Time ............................................... 8-8
Over Modulation .............................................................. 8-12
Update Modes ...................................................................... 8-15
Single Update ................................................................... 8-15
Double Update ................................................................. 8-15
Configurable Polarity ............................................................ 8-15
PWM Pins and Signals .......................................................... 8-16
Crossover ......................................................................... 8-16
PWM Accuracy ..................................................................... 8-17
PWM Registers .......................................................................... 8-18
Duty Cycles .......................................................................... 8-19
Output Enable ...................................................................... 8-20
Programming Example ................................................................ 8-21
S/PDIF TRANSMITTER/RECEIVER
AES3/SPDIF Stream Format ......................................................... 9-2
Subframe Format .................................................................... 9-3
Channel Coding ..................................................................... 9-5
Preambles ............................................................................... 9-6
S/PDIF Transmitter ...................................................................... 9-7
Channel Status ........................................................................ 9-9
SRU1 Signals for the S/PDIF Transmitter .............................. 9-10