ADSP-21368 SHARC Processor Hardware Reference xv
Contents
Packing Mode 10 .............................................................. 7-10
Packing Mode 01 .............................................................. 7-11
Packing Mode 00 .............................................................. 7-11
Clocking Edge Selection ........................................................ 7-12
Hold Input ............................................................................ 7-12
PDAP Strobe ......................................................................... 7-14
FIFO Control and Status ............................................................ 7-15
FIFO to Memory Data Transfer ................................................... 7-16
IDP Transfers Using the Core ................................................ 7-17
Starting an Interrupt-Driven Transfer ................................ 7-18
Core Transfer Notes .......................................................... 7-19
IDP Transfers Using DMA .................................................... 7-20
Simple DMA .................................................................... 7-20
Ping-Pong DMA ............................................................... 7-22
DMA Transfer Notes ......................................................... 7-25
DMA Channel Parameter Registers ........................................ 7-27
IDP (DAI) Interrupt Service Routines for DMAs ................... 7-28
FIFO Overflow ..................................................................... 7-30
Input Data Port Programming Example ....................................... 7-31
PULSE WIDTH MODULATION
PWM Implementation .................................................................. 8-1
PWM Waveforms .................................................................... 8-1
Edge-Aligned Mode ............................................................ 8-2
Center-Aligned Mode .......................................................... 8-3
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