ADSP-21368 SHARC Processor Hardware Reference xix
Contents
SRU Programming .............................................................. 10-22
SRC Mute-Out Interrupt ..................................................... 10-23
Sample Rate Ratio ............................................................... 10-23
Programming Summary ....................................................... 10-23
UART PORT CONTROLLER
Serial Communications ............................................................... 11-2
UART Control and Status Registers ............................................. 11-3
UARTxLCR Registers ............................................................ 11-3
UARTxLSR Register .............................................................. 11-4
UARTxTHR Register ............................................................ 11-4
UARTxRBR Register ............................................................. 11-5
UARTxIER Register .............................................................. 11-7
UARTxIIR Register ............................................................... 11-9
UARTxDLL and UARTxDLH Registers .............................. 11-11
UARTxSCR Register ........................................................... 11-12
UARTxMODE Register ...................................................... 11-13
I/O Mode ................................................................................. 11-13
Packing Mode ........................................................................... 11-15
TWO WIRE INTERFACE CONTROLLER
Overview .................................................................................... 12-1
Architecture ................................................................................ 12-2
Register Descriptions .................................................................. 12-4
TWI Master Internal Time Register ....................................... 12-4
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