Contents
xx ADSP-21368 SHARC Processor Hardware Reference
TWIDIV Register ................................................................. 12-5
Slave Mode Control Register ................................................. 12-5
Slave Mode Address Register ................................................. 12-6
Slave Mode Status Register .................................................... 12-6
Master Mode Control Register .............................................. 12-6
Master Mode Address Register ............................................... 12-6
Master Mode Status Register ................................................. 12-7
FIFO Control Register .......................................................... 12-7
FIFO Status Register ............................................................. 12-7
Interrupt Source Register ...................................................... 12-7
Interrupt Enable Register ...................................................... 12-8
8-Bit Transmit FIFO Register ................................................ 12-8
16-Bit Transmit FIFO Register .............................................. 12-8
8-Bit Receive FIFO Register .................................................. 12-9
16-Bit Receive FIFO Register .............................................. 12-10
Data Transfer Mechanics ........................................................... 12-10
Clock Generation and Synchronization ................................ 12-11
Bus Arbitration ................................................................... 12-12
Start and Stop Conditions ................................................... 12-12
General Call Support .......................................................... 12-14
Fast Mode ........................................................................... 12-14
Programming Examples ............................................................ 12-15
General Setup ..................................................................... 12-15
Slave Mode ......................................................................... 12-15