ADSP-21368 SHARC Processor Hardware Reference xxi
Contents
Master Mode Clock Setup ................................................... 12-17
Master Mode Transmit ........................................................ 12-17
Master Mode Receive ........................................................... 12-18
Repeated Start Condition .................................................... 12-19
Transmit/Receive Repeated Start Sequence ....................... 12-19
Receive/Transmit Repeated Start Sequence ....................... 12-21
Electrical Specifications ............................................................. 12-22
PRECISION CLOCK GENERATORS
Clock Outputs ............................................................................ 13-3
Frame Sync Outputs ................................................................... 13-4
Normal Mode ........................................................................ 13-5
Bypass Mode ......................................................................... 13-6
Frame Sync Output Synchronization With an External Clock ...... 13-7
Frame Sync ........................................................................... 13-8
Phase Shift .................................................................................. 13-9
Phase Shift Settings ............................................................. 13-10
Pulse Width ........................................................................ 13-10
Bypass Mode ....................................................................... 13-12
Bypass as a Pass Through ................................................. 13-12
Bypass as a One-Shot ...................................................... 13-13
Programming Examples ............................................................. 13-14
PCG Setup for I2S or Left-Justified DAI .............................. 13-15
Clock and Frame Sync Divisors PCG Channel B .................. 13-20
PCG Channel A and B Output Example .............................. 13-23
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