Analog Devices SHARC ADSP-21368 - Page 22

Contents
xxii ADSP-21368 SHARC Processor Hardware Reference
SYSTEM DESIGN
Processor Pin Descriptions .......................................................... 14-2
Pin Multiplexing ................................................................... 14-2
Choosing EP Data Mode .................................................. 14-6
Interrupt and Timer Pins ...................................................... 14-8
Core-Based Flag Pins ............................................................. 14-8
Programming Flags ........................................................... 14-9
RESETOUT/CLKOUT/RUNRSTIN ............................. 14-12
JTAG Interface Pins ............................................................ 14-12
Clock Derivation ...................................................................... 14-13
Power Management Control Register ................................... 14-14
PLL Programming Examples ........................................... 14-16
Phase-Locked Loop Startup ................................................. 14-19
RESET and CLKIN ............................................................ 14-20
Running Reset (ADSP-2137x) ............................................ 14-22
System Design Considerations ........................................ 14-23
Running Reset Control Register (RUNRSTCTL) ............ 14-25
Programming The RUNRSTCTL Register ...................... 14-26
Reset Generators ............................................................. 14-27
Timing Specifications .......................................................... 14-28
Input Synchronization Delay ............................................... 14-32
Conditioning Input Signals ....................................................... 14-32
RESET Input Hysteresis ...................................................... 14-33