ADSP-21368 SHARC Processor Hardware Reference 13-15
Precision Clock Generators
PCG Setup for I
2
S or Left-Justified DAI
This example shows how to set up two precision clock generators using
the S/PDIF receiver and an asynchronous sample rate converter (SRC) to
interface to an external audio DAC. In this example an input clock
(CLKIN) of 33.330 MHz is assumed and the PCG is configured to provide
a fixed SRC/DAC output sample rate of 65.098 kHz. The input to the
S/PDIF receiver is typically 44.1 kHz if supplied by a CD player but can
also be from another source at any nominal sample rate from about 22
kHz to 192 kHz.
Three synchronous clocks are required: a framesync (FSYNC; FS), a master
clock (PCGx_CLK; 256 × FS), and a serial bit clock (SCLK; 64 × FS). Since
each PCG has only two outputs, this example requires two PCGs. Fur-
thermore, because the digital audio interface requires a fixed-phase
relation between SCLK and FSYNC, these two outputs should come from one
PCG while the master clock comes from the other.
The CLKIN = 33.330 MHz is divided by the two PCGs to provide the three
synchronous clocks — PCGx_CLK, SCLK, and FSYNC for the SRCs and exter-
nal DAC. These divisors are stored in 20-bit fields in the PCG_CTL
registers. For more information, see “Precision Clock Generator Registers”
on page A-155.
The integer divisors for several possible sample rates based on 33.330
MHz
CLKIN are shown in Table 13-2.
To Next Page
Loading...
Need help?
General
