Analog Devices SHARC ADSP-21368 - Page 24

Contents
xxiv ADSP-21368 SHARC Processor Hardware Reference
DMA Stalls ......................................................................... 14-56
IOP Buffer Stalls ................................................................. 14-56
REGISTER REFERENCE
I/O Processor Registers ................................................................. A-2
Notes on Reading Register Drawings ....................................... A-3
System Control Register (SYSCTL) ......................................... A-5
System Status Register (SYSTAT) ............................................ A-9
External Port Registers ................................................................ A-10
External Port Control Register (EPCTL) ............................... A-10
External Port DMA Control Registers (DMACx) ................... A-14
AMI Control Registers (AMICTLx) ...................................... A-17
AMI Status Register (AMISTAT) ........................................... A-20
SDRAM Control Register (SDCTL) ...................................... A-21
SDRAM Control Status Register (SDSTAT) .......................... A-26
SDRAM Refresh Rate Control Register (SDRRC) .................. A-26
Memory-to-Memory DMA Register ............................................ A-28
Serial Port Registers .................................................................... A-29
SPORT Serial Control Registers (SPCTLx) ............................ A-29
SPORT Multichannel Control Registers (SPMCTLx) ............ A-40
SPORT Transmit Buffer Registers (TXSPx) ........................... A-43
SPORT Receive Buffer Registers (RXSPx) .............................. A-44
SPORT Divisor Registers (DIVx) .......................................... A-44
SPORT Count Registers (SPCNTx) ...................................... A-45
SPORT Active Channel Select Registers (SPxCSy) ................. A-46