Analog Devices SHARC ADSP-21368 - Page 25

ADSP-21368 SHARC Processor Hardware Reference xxv
Contents
SPORT Compand Registers (SPxCCSy) ................................ A-47
SPORT Error Control Register (SPERRCTLx) ...................... A-48
SPORT Error Status Register (SPERRSTAT) ......................... A-49
SPORT DMA Index Registers (IISPx) ................................... A-50
SPORT DMA Modifier Registers (IMSPx) ............................ A-50
SPORT DMA Count Registers (CSPx) ................................. A-51
SPORT Chain Pointer Registers (CPSPx) .............................. A-51
Serial Peripheral Interface Registers ............................................. A-52
SPI Control Registers (SPICTL, SPICTLB) .......................... A-52
SPI Port Status (SPISTAT, SPISTATB) Registers ................... A-56
SPI Port Flags Registers (SPIFLG, SPIFLGB) ........................ A-58
SPI Receive Buffer Registers (RXSPI, RXSPIB) ..................... A-59
RXSPI Shadow Registers
(RXSPI_SHADOW, RXSPIB_SHADOW) ......................... A-59
SPI Transmit Buffer Registers (TXSPI, TXSPIB) ................... A-59
SPI Baud Rate Registers (SPIBAUD, SPIBAUDB) ................ A-60
SPI DMA Registers .............................................................. A-61
SPI DMA Configuration Registers (SPIDMAC,
SPIDMACB) ................................................................ A-62
SPI DMA Start Address Registers (IISPI, IISPIB) .............. A-64
SPI DMA Address Modify Registers (IMSPI, IMSPIB) ..... A-64
SPI DMA Word Count Registers (CSPI, CSPIB) .............. A-64
SPI DMA Chain Pointer Registers (CPSPI, CPSPIB) ........ A-65
Input Data Port Registers ........................................................... A-65
Input Data Port Control Register 0 (IDP_CTL0) .................. A-66